The present invention relates to a technique for improving the reliability of nonvolatile memories, and more particularly to a technique that can be effectively applied to reducing damage to memory cells when erasing data therein.
In recent years, along with the increasingly widespread use of mobile devices including mobile telephones above all, the requirements for larger data capacities and reduced costs are becoming more stringent at a rapid pace. One of the known techniques to meet this new requirement for larger capacities is a multiple value storage technique by which a plurality of threshold voltage levels are set for each memory cell and data of two bits or more each are stored, embodied in multiple value flash memories.
The present inventors applied for a patent regarding operations to write into a multiple value flash memory, identified as the Japanese Unexamined Patent Publication No. 2002-109891 (Patent Reference 1). In this application, the inventors describe a technique by which, in writing into a flash memory, a voltage pulse of a short duration is applied to the control gate of a memory cell in an erased state a plurality of times as the write voltage pulse to be first applied to the memory cell in order to prevent the phenomenon of accidental excess writing (erratic error).
It has been found that the erratic error phenomenon more frequently occurs when a write voltage pulse is first written into a memory cell in an erased state. This means that, by shortening the duration of the write voltage pulse first applied to a memory cell in an erased state, it is made possible to reduce the electric charge accumulated in the charge accumulation area of the memory cell by an FN tunnel phenomenon resulting from a high electrical field applied between the channel area and the control gate of the memory cell, and thereby to prevent a substantial variation in threshold voltage even if an erratic error phenomenon arises as mentioned above.
Another technique against the erratic error phenomenon in write operations is also disclosed in the Japanese Unexamined Patent Publication No. Hei 10(1998)-27486 (Patent Reference 2). To compare Patent Reference 1 and Patent Reference 2, the direction in which the threshold voltage varies in a write operation according to Patent Reference 1 is the same as the direction in which the threshold voltage varies in an erase operation according to Patent Reference 2, and the direction in which the threshold voltage varies in an erase operation according to Patent Reference 1 is the same as the direction in which the write threshold voltage varies according to Patent Reference 2.
This reveals that, irrespective of the varying direction of the threshold voltage, an erratic error phenomenon can occur in a write operation.
On the other hand, an operation to erase data in a flash memory is accomplished by applying an erase voltage to the control gates of memory cells in each erasion unit, and causing the FN tunnel phenomenon occurring between the channel areas and the control gates of the memory cells to pull the electric charges accumulated in the charge accumulation areas of the memory cells towards the channel areas.
Patent Reference 1: Japanese Unexamined Patent Publication No. 2002-109891 (U.S. Pat. No. 6,490,201)
Patent Reference 2: Japanese Unexamined Patent Publication No. Hei 10(1998)-27486 (U.S. Pat. No. 5,959,882)